As semiconductor technology progresses, shrinking device dimensions has become an increasingly complex task. One approach to overcome these difficulties is by using vertical integration of multiple semiconductor devices (chips). This allows larger number of devices per unit (e.g. in memory applications), as well as integration of chips of different functionality thus allowing better performance of a hybrid system (e.g. sensor, processor and memory).
One method under development for vertical integration is based on Through Silicon Via (TSV). TSV is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSV is a high performance technique to create 3D packages and 3D integrated circuits (as compared to its alternatives such as package-on-package), because the density of vias is substantially higher and the length of the connections is shorter. According to TSV, conducting pillars are formed within a silicon substrate, later to be used for contacting successive chips. To connect electrically the components in different layers, TSV technology is used to provide the electrical interconnect and to provide mechanical support. In TSV technology, a via is fabricated in a silicon chip with different active integrated circuit devices or other devices fabricated by a semiconductor process, and the via is filled with metal such as Cu, Au, W, solders, or a highly-doped semiconductor material such as polysilicon. Multiple components provided with such vias are then stacked and bonded together.
One critical step in the TSV process is via formation, in which a pattern of contacts is etched into the silicon. In order to maintain the required via quality, it is essential to control both the depth and profile of the vias.